This section covers three popular examples, and Figure 8. Category 5 Unsheilded Twisted pair "Cat5" : The frst medium is twisted pairs of copper wires. These are two insulated wires, each about 1 mm thick. They are twisted together to reduce electrical interference, since two parallel lines form an antenna but a twisted pair does not. As they can transfer a few megabits per second over several kilometers without amplification, twisted pair were the mainstay of the telephone system. Telephone companies bundled together and sheathed many pairs coming into a building.

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Differentiate desktop, Embedded and server computers? What are Wheatstone benchmarks? What are the different level of program used for evaluating the performance of a machine? What is SPEC? What is a kernel? Mention the difference between desktop, Embedded and server benchmarks? Define Total execution time Define Weighted execution time Define Normalized execution time State Amdahls law Define Speedup?

Give the CPU performance equation and define the following a. CPI b. Instruction count What is the principle of locality? What are the various classes of instruction set architecture? What is Little Endian and big Endian? What is effective address and pc relative address? What are the various addressing modes? What are modulo and bit reverse addressing modes? Comment the type and size of operands? Explain the operand for media and signal processing Give the various categories of instruction operators with example for each?

Commend the operation for media and signal processing? What are the different type of control flow instructions? Give the major methods of evaluating branch condition, their advantages and disadvantages Explain instruction coding and its type? What are the various compiler optimization available? What is a media processor? Give example What is a vector processor? What is Flynns taxonomy? Explain the various methods by which data level parallelism is obtained?

Differentiate von Neumann and hardware architecture. What is pipelining? What are the basic of RISC instruction set architecture?

What are the different stages of pipelined architecture? Briefly describe basic performance issues in pipelining? What are hazards? Mention its types? How data hazards can be minimized? What are structural hazards? What are control hazards? How is pipelining implemented?

What makes pipelining hard to implement? Mention the various exceptions and methods to deal with exceptions? What is score boarding? What are linear pipeline processors? What is clock skewing? Differentiate static and dynamic pipelining?

What are non linear pipeline processor? What is latency? What is reservation table? What are forbidden and permissible latencies?

What are contact cycle? What is collision vector? Explain pipeline throughput and efficiency How do you compute pipeline CPI? What is a basic block? What is ILP? What are forwarding and bypassing techniques?

What is loop-level parallelism? What are the various dependences? How to overcome it? How to avoid hazards? What are the different name dependences? What is a control dependence? What is a data dependence? What is dynamic scheduling?

Compare dynamic scheduling with static pipeline scheduling? Differentiate in-order and out-of-order execution of instruction? What is imprecise exception? Explain Tomasulos algorithm briefly? Explain WAR hazards? Explain WAW hazards? Explain RAW hazards? What is a reservation station? Give the merits of Tomasulos algorithm? How to remove control dependences? Compare 1 bit and 2 bit prediction schemes? Give the merits and demerits of 2 bit prediction scheme? What are correlating branch predictors?

What is register renaming? What is commit stage? How to take advantages of more ILP with multiple issue? Compare superscalar and VLIW processors? What are statically scheduled superscalar processors? How multiple instruction issue is handled by dynamic scheduling? What are limitations of ILP? Explain P6 micro architecture? What is thread level parallelism TLP? Give the practical limitation on exploiting more ILP?

What is the role of compiler in exploiting ILP? Give the typical latencies of FP operations and loads and stores. What is loop unrolling? Give the summary of loop unrolling and scheduling. What is register pressure? How loop unrolling and pipeline scheduling can be used with static multiple issue?

What is a static branch prediction?


CS2354 Advanced Computer Architecture

Cache Performance And various cache optimization categories. The first-level cache can be small enough to match the clock cycle time of the fast CPU and the second-level cache can be large enough to capture many accesses that would go to main memory, thereby the effective miss penalty. The definition of average memory access time for a two-level cache. As you would expect, for the first-level cache it is equal to Miss rateL1 and for the second-level cache it is Miss rateL2. Global miss rateā€”The number of misses in the cache divided by the total num-ber of memory accesses generated by the CPU.


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Differentiate desktop, Embedded and server computers? What are Wheatstone benchmarks? What are the different level of program used for evaluating the performance of a machine? What is SPEC? What is a kernel?

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